DocumentCode
2704205
Title
SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits]
Author
Jang, Wonjin ; Marti, Alain J.
Author_Institution
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
fYear
2005
fDate
14-16 March 2005
Firstpage
156
Lastpage
165
Abstract
This paper addresses the issue of single-event upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present simplified SEU-tolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comparator and show SPICE-simulation results.
Keywords
CMOS logic circuits; asynchronous circuits; buffer circuits; comparators (circuits); fault tolerance; logic design; radiation hardening (electronics); CMOS; SEU-tolerant QDI circuits; SEU-tolerant buffer; one-bit comparator; quasi delay-insensitive asynchronous circuits; single-event upset; Circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on
ISSN
1522-8681
Print_ISBN
0-7695-2305-6
Type
conf
DOI
10.1109/ASYNC.2005.30
Filename
1402057
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