DocumentCode
2704230
Title
A multiplexer based test method for self-timed circuits
Author
Beest, Frank Te ; Peeters, Ad
Author_Institution
Handshake Solutions, Philips Technol. Incubator, Eindhoven, Netherlands
fYear
2005
fDate
14-16 March 2005
Firstpage
166
Lastpage
175
Abstract
A new test method for self-timed circuits is presented that only uses multiplexers to make the majority of combinational feedback loops testable. Combinational feedback loops are problematic for testing, since they introduce sequential behavior in a circuit. Traditionally feedback loops are broken with scan latches or event scan flip-flops, which causes not only a large area overhead, but also has a large impact on performance. The method we present significantly reduces the cost of testing a self-timed circuit, while it retains all the benefits of traditional scan test methods. Most importantly, the method remains fully compatible with standard combinational test pattern generation tools and provides up to 100% stuck-at fault coverage. With the presented test method, it becomes cost effective to use scan test for a self-timed circuit without the need to add new specialized cells to a standard cell library.
Keywords
asynchronous circuits; boundary scan testing; circuit feedback; combinational circuits; logic design; logic testing; multiplexing equipment; sequential circuits; combinational feedback loop testing; combinational test pattern generation tools; multiplexer based test method; scan test methods; self-timed circuits; sequential circuits; shift register optimization; stuck-at fault coverage; Automatic testing; Circuit testing; Costs; Feedback circuits; Feedback loop; Flip-flops; Latches; Multiplexing; Sequential analysis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on
ISSN
1522-8681
Print_ISBN
0-7695-2305-6
Type
conf
DOI
10.1109/ASYNC.2005.5
Filename
1402058
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