New prospects for clocking synchronous and quasi-asynchronous systems

Summary form only given. Global clock distribution faces increasing challenges in distributing low-jitter clocks in the presence of power-supply noise. Resonant clocking techniques, which resonate the clock capacitance with on-chip inductance, promise to ease these constraints. Topologies that act as either resonant loads or free-running oscillators are described. Asynchronous techniques promise to eliminate clocks entirely. Proponents may argue that this eliminates issues associated with clock skew, jitter and power. We argue a more realistic viewpoint that recognizes that asynchronous systems must still distribute "control signals." Variation in the delay of these signals (skew and jitter) presents the same synchronization overhead as clock skew and jitter in synchronous systems. While fully asynchronous high-speed processors do not seem imminent, there is a growing opportunity for significant benefit from GALS (globally asynchronous locally synchronous) concepts on multiprocessor chips. Robust low-latency asynchronous interfaces could give us many of the benefits of asynchronous design while still leveraging the huge investment in synchronous processor design, methodology, and experience.