A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

Author

Okamura, Hiroyuki ; Toyoshima, Hisashi ; Takeda, Kenji ; Oguri, T. ; Nakamura, Shigenari ; Takada, Masumi ; Imai, Koichi ; Kinoshita, Yuta ; Yoshida, Hiroyuki ; Yamazaki, Tsutomu

Author_Institution

Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

306

Lastpage

307

Abstract

While an ECL-CMOS SRAM achieves high speed and high integration density it consumes a lot of power. This paper describes a non-threshold logic (NTL) CMOS SRAM macro that offers lower power consumption and increased stability while maintaining speed. This SRAM macro is implemented on a 0.4 /spl mu/m BiCMOS process and includes an NTL decoder with a stable supply voltage generator, a CMOS memory cell with p-channel MOS access transistors and an automatic bit-line voltage swing controller.

Keywords

BiCMOS memory circuits; SRAM chips; cellular arrays; circuit stability; integrated circuit design; 0.4 micron; 1 W; 1 ns; 2.5 V; 32 Kbit; BiCMOS process; MOS access transistors; NTL-CMOS SRAM macro; automatic bit-line voltage swing controller; memory cell; nonthreshold logic; p-channel access transistors; power consumption; stability; stable supply voltage generator; Automatic generation control; Automatic voltage control; BiCMOS integrated circuits; CMOS logic circuits; CMOS process; Decoding; Energy consumption; MOSFETs; Random access memory; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535567

Filename

535567