Title :
Implementation of TS De-multiplexer with FPGA in DVB_IP Gateway for Network TV
Author :
He, Yihu ; Zhou, Jun ; Zhou, Yuanhua
Author_Institution :
Inst. of Image Commun. & Inf. Process., Shanghai Jiao Tong Univ.
fDate :
Oct. 30 2005-Nov. 2 2005
Abstract :
An FPGA-based de-multiplexing architecture is realized in DVB_IP gateway for network TV broadcasting on the dedicated real-time and bandwidth-varying T-bit router, T-bit switch, T-bit transfer (3Tnet) network. The main purpose of this architecture is to convert the multi-program transport stream (MPTS) with bit rate up to 96 Mbps into six single program transport streams (SPTS), which can be encapsulated into real-time transport protocol (RTP) packets in compliance with RFC2250. To prevent loss of presentation synchronization, program clock reference (PCR) correction is implemented in accordance with tolerance defined in ISO/IEC 13818-1. The cooperation between DVB_IP gateway and IP set top box works well and the playout is quite satisfactory
Keywords :
IP networks; demultiplexing; digital video broadcasting; field programmable gate arrays; internetworking; routing protocols; synchronisation; transport protocols; video streaming; DVB_IP gateway; FPGA-based demultiplexing architecture; IP set top box; MPTS; PCR; RFC2250; RTP packet; SPTS; T-bit switch; T-bit transfer network; bandwidth-varying T-bit router; field programmable gate array; multiprogram transport stream; network TV broadcasting; presentation synchronization; program clock reference correction; real-time transport protocol; single program transport stream; Bit rate; Clocks; Digital video broadcasting; Field programmable gate arrays; IEC standards; ISO standards; Switches; Synchronization; TV broadcasting; Transport protocols; 3Tnet; DVB_IP Gateway; FPGA; Network TV; PCR correction;
Conference_Titel :
Multimedia Signal Processing, 2005 IEEE 7th Workshop on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9288-4
Electronic_ISBN :
0-7803-9289-2
DOI :
10.1109/MMSP.2005.248571
