A VLSI architecture for ATM algorithm-agile encryption

In this paper a VLSI architecture is proposed for an algorithm-agile encryptor for ATM networks. The architecture is based on a circular sorting queue that buffers and switches incoming cells to the appropriate encryption pipelines. It also handles multicast cells that require different encryption algorithms for different destinations. Delay and loss priority are analyzed for multi-class traffic processed through the encryptor. The analysis results are necessary to size the buffer properly and to choose an appropriate priority scheme. An ASIC prototype of the sorting queue that supports an aggregate traffic rate of up to 21.2 Gbps is also presented