Test challenges for 3D-SICs: All the old, most of the recent, and then some new!

Author

Marinissen, Eruk Jan

Author_Institution

IMEC vzw, Leuven, Belgium

fYear

2009

fDate

1-6 Nov. 2009

Firstpage

1

Lastpage

1

Abstract

Three-dimensional stacked integrated circuits (3D-SICs) are coming soon to a micro-electronics product near you! The test community needs to prepare itself to be able to test this new generation of ´super chips´. Obviously, 3D-SICs require all the basic test technology with respect to test generation, design-for-test, wafer probe, handling, and test equipment. In addition, 3D-SICs require most of the recently-developed advanced test technology as well: (small) delay-faults, VLV tests, IEEE-1500, RPCT, TDC, BIST, KGD, adaptive test, diagnosis, PFA, yield learning... Test technology has advanced beyond simple stuck-at pattern generation, scan-only DfT, and the traditional test cell; it requires at least an annual trip to ITC for a DfT or test engineer to stay up-to-date with all the latest developments!

Keywords

built-in self test; design for testability; integrated circuit testing; 3D stacked integrated circuits; BIST; IEEE-1500; KGD; PFA; RPCT; TDC; VLV tests; adaptive test; delay-faults; microelectronics product; scan-only design-for-test; stuck-at pattern generation; test equipment; test generation; wafer probe; yield learning; Automatic testing; Circuit testing; Delay; Design for testability; Integrated circuit technology; Marine technology; Probes; Semiconductor device modeling; Test equipment; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2009. ITC 2009. International

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-4868-5

Electronic_ISBN

978-1-4244-4867-8

Type

conf

DOI

10.1109/TEST.2009.5355674

Filename

5355674