Title :
Accurate resource estimation algorithms for behavioral synthesis
Author :
Katkoori, Srinivas ; Vemuri, Ranga
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Given a scheduled data flow graph the functional, storage, and interconnect (multiplexors) resources are analytically estimated taking into account the effects of post-scheduling tasks. Complexity of the controller implementation is also estimated. The novelty of this work lies in predicting the effects of the post-scheduling task on the final amount of resources, the effects of data path resource optimization on the controller complexity. Experimental results show high correlation between estimated and actual numbers
Keywords :
data flow graphs; high level synthesis; programmable logic arrays; scheduling; behavioral synthesis; controller implementation; data path resource optimization; interconnect resources; multiplexors; post-scheduling tasks; resource estimation algorithms; scheduled data flow graph; Control system synthesis; Feedback; Parallel processing; Performance analysis; Processor scheduling; Registers; Resource management; Scheduling algorithm; Signal generators; Upper bound;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757449
