Title :
Assessing defect coverage of memory testing algorithms
Author :
Kim, Vonkyoung ; Chen, Tom
Author_Institution :
Sun Microsyst., Palo Alto, CA, USA
Abstract :
This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2×2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms
Keywords :
CMOS memory circuits; SRAM chips; circuit simulation; fault diagnosis; integrated circuit testing; CMOS defects; IFA tool; SRAM layout; circuit simulations; defect coverage; memory testing algorithms; Algorithm design and analysis; Bridge circuits; CMOS memory circuits; Circuit faults; Circuit simulation; Circuit testing; Fault detection; Performance evaluation; Random access memory; Sun;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757450
