Title :
Exploiting test resource optimization in data path synthesis for BIST
Author :
Li, Xiaowei ; Cheung, Paul Y S
Author_Institution :
Dept. of Comput. Sci. & Technol., Beijing Univ., China
Abstract :
Area and test time are two major overheads encountered during data path synthesis for BIST. This paper presents an attempt towards testability enhancement in data path BIST synthesis by considering two factors simultaneously. It is achieved by incorporating two testability constraints in data path synthesis. Experimental results are presented to demonstrate the effectiveness of the proposed (data path) BIST synthesis approach
Keywords :
VLSI; automatic test pattern generation; built-in self test; design for testability; integer programming; integrated circuit testing; linear programming; optimisation; BIST; area; data path synthesis; overheads; test resource optimization; test time; testability constraints; testability enhancement; Benchmark testing; Built-in self-test; Computer science; Concurrent computing; Costs; Integer linear programming; Logic testing; Performance evaluation; System testing; Test pattern generators;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757451
