Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

A novel comparator placing scheme and reference ladder concept are presented for flash analog-to-digital converters (ADC), that minimize the dynamic reference voltage distortions at high signal speed. No track-and-hold or time interleaving is used in the ADC, which reduces the design complexity and minimizes the conversion latency. The data input signal is buffered by an emitter follower (EF) and distributed by a passive transmission line (TML) tree to the comparators. The EF and comparators are systematically optimized with respect to the energy efficiency and design considerations for the trade off between dynamic linearity and power dissipation are given in detail. The TML tree is designed such that in spite of inhomogeneous loading by the comparators equal transfer functions are achieved along all paths. The ADC achieves without calibration or correction an effective resolution beyond 3.7 bits up to 10 GHz signal frequency and 20 GS/s sampling. With 1.0 W of power dissipation the conversion efficiency is 3.9 pJ per conversion step, which sets a record for single-core ADCs beyond 10 GS/s Nyquist rate.