Switching noise in ECL packaging and interconnect systems

Switching noise in ECL (emitter coupled logic) circuits and their associated packaging and interconnect systems has been studied. The relative effectiveness of including bypass capacitors, complementary outputs, DC termination planes, and active regulation was evaluated as a function of edge rate and packaging parasitics. The simulation of a single ECL gate is discussed. For more than one gate switching simultaneously the functional dependence of the noise on the number of switching gates depends on the specific system design. An example of multiple switching gates is presented