DocumentCode :
2704786
Title :
Running scan test on three pins: yes we can!
Author :
Moreau, Jocelyn ; Droniou, Thomas ; Lebourg, Philippe ; Armagnat, Paul
Author_Institution :
Imaging Div., STMicroelectronics, Grenoble, France
fYear :
2009
fDate :
1-6 Nov. 2009
Firstpage :
1
Lastpage :
10
Abstract :
Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three years ago, people asked for a solution to run industrial structural test on such complex devices could though only reply ¿impossible¿ or ¿Do It Yourself¿. STMicroelectronics did not escape the rule. An internal development and a partnered development were thus successively launched to address this issue. This article proposes to examine all the why and how of these developments along with the good results obtained during that time, in terms of test cost improvement, area overhead in silicon, design flow updates and industrialization process. Getting all sensors designed today equipped and test data volume (and time) improvements in the range of 25X to 30X just took that three years time. Now that the solution is industrially available, it´s also time to share and look at the future of industrial scan test on three pins...
Keywords :
integrated circuit testing; STMicroelectronics; digital pins; running scan test; CMOS image sensors; Circuit testing; Clocks; Costs; Design for testability; Graphics; Packaging; Pins; Power supplies; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
Type :
conf
DOI :
10.1109/TEST.2009.5355693
Filename :
5355693
Link To Document :
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