• DocumentCode
    2705208
  • Title

    Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning

  • Author

    Chang, Chia Ling Lynn ; Wen, Charles H P ; Bhadra, Jayanta

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2009
  • fDate
    1-6 Nov. 2009
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    A learning-and-filtering algorithm is proposed to uncover cross-timeframe state-pair constraints for speeding up SAT solving of bounded sequential equivalence checking (BSEC) problems. First, relaxed Boolean functions for flip-flop states at respective timeframes are learned from a small number of simulation data to derive the initial set of the state-pair candidates. Next, each candidate is examined and removed if both values in such a candidate have coordinately appeared during the simulation. Then, the validity of the remaining candidates is checked against the corresponding augmented circuit. Last, only the true constraints are annotated to the BSEC problems to facilitate SAT solving. All benchmark circuits are synthesized under 10 configurations to produce different BSEC problems. Experimental results show that the new SAT solving runs 2-order faster in average compared to using MiniSAT 2.0 only. Moreover, given a time bound, the total number of timeframes can increase by 8X-20X on 4 larger circuits after applying the proposed framework.
  • Keywords
    Boolean functions; VLSI; computability; filtering theory; flip-flops; integrated circuit design; BSEC problems; Boolean satisfiability; SAT solving; Speeding VLSI; augmented circuit; benchmark circuits; bounded sequential equivalence checking problems; cross-timeframe state-pair constraints; data learning; flip-flop states; learning-and-filtering algorithm; relaxed Boolean functions; state-pair candidates; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit simulation; Constraint optimization; Electronic design automation and methodology; Filtering; Flip-flops; Logic; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2009. ITC 2009. International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-4868-5
  • Electronic_ISBN
    978-1-4244-4867-8
  • Type

    conf

  • DOI
    10.1109/TEST.2009.5355713
  • Filename
    5355713