An Area Efficient of 0.187Mu LNA Using Power Constraint Method

This paper presents the design for Low Noise Amplifier (LNA) using Silterra 0.18Mu technology and it based on W-CDMA standard application. The LNA function is to amplify extremely low noise signal without adding noise and also preserving required signal to noise ratio of the system at extremely low power level. Cadence design tool is used to optimize the simulation performance based on resistor and capacitor distributed. The used of power constrained method to provide an area-efficient architecture for effective design at Silterra 0.18Mu CMOS technology. Result for S11 is 13.12dB and the frequencies are at 2.08GHz while S21 is observed to be -20dB and these values show that the resistance at the input of LNA is very close to 503.