Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing

A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including periodic jitter, random jitter and data dependent jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5 Gb/s timing generator and was fabricated by a 90 nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2 mm² and 43.8 mW respectively.