SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL

A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented