Bipolar device design for circuit performance optimization

Author

Chiang, Shang-yi ; Pettengill, Don ; Voorde, Paul Vande

Author_Institution

Hewlett Packard Corp., Palo Alto, CA, USA

fYear

1990

fDate

17-18 Sep 1990

Firstpage

172

Lastpage

179

Abstract

Processes such as polysilicon emitter, various self-alignment schemes, and deep trench isolation have led to significant improvements in intrinsic speed and reductions in parasitic RC elements in silicon BJT (bipolar junction transistor) devices. Some basic physical limitations involved in further scaling the intrinsic device vertical profile for silicon BJTs are discussed. Also presented is a review of recent developments in silicon-based heterojunction bipolar transistors which have the potential of overcoming some of the basic limitations in homojunction BJTs

Keywords

bipolar integrated circuits; bipolar transistors; elemental semiconductors; heterojunction bipolar transistors; silicon; BJT; HBT; Si; bipolar device design; bipolar junction transistor; circuit performance optimization; heterojunction bipolar transistors; intrinsic device vertical profile; intrinsic speed; parasitic RC elements; scaling; Circuit optimization; Delay; Design optimization; Integrated circuit interconnections; Power dissipation; Power supplies; Silicon; Transistors; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1990.171156

Filename

171156