Process technologies for a 16 ns high speed 1 Mb CMOS EPROM

Author

Matsukawa, N. ; Araki, H. ; Narita, K. ; Masuda, K. ; Atsumi, S. ; Kuriyama, M. ; Imamiya, K.

fYear

1990

fDate

4-7 June 1990

Firstpage

127

Lastpage

128

Abstract

An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability. Process and device parameters are summarized. An 0.8-μm N-well CMOS, 1 poly Si+1 MoSi polycide double metal technology is used. To fabricate 5-V and 12.5-V high-voltage NMOS and PMOS transistors simultaneously, masked lightly-doped-drain structures are used

Keywords

CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 0.8 micron; 1 Mbit; 12.5 V; 16 ns; 5 V; Al; MoSi; N-well CMOS; NMOS transistors; PMOS transistors; Si; cell structure; data retention; data retention reliability; erasability; folded word lines; high-speed access; masked lightly-doped-drain structures; metallization process; polycide double metal technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on

Conference_Location

Honolulu, Hawaii, USA

Type

conf

DOI

10.1109/VLSIT.1990.111041

Filename

5727501