Title :
A 2 ns 16 K ECL RAM with reduced word line voltage swing
Author :
Nakase, Yasunobu ; Ikeda, Takashi ; Mashiko, K. ; Kayano, S.
Abstract :
A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation
Keywords :
SRAM chips; VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated memory circuits; 16 kbit; 2 ns; ECL RAM; emitter coupled logic; fast write operation; faster read operation; large ISR; reduced word line voltage swing; reduced word line voltage swing circuit; small reverse mode current gain; write operation;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111088
