Title :
A 1 V operating 256-Kbit full CMOS SRAM
Author :
Sekiyama, A. ; Seki, T. ; Nagai, S. ; Iwase, A. ; Suzuki, N. ; Hayasaka, M.
Abstract :
A full CMOS six-transistor memory cell was fabricated with single-polysilicon, double-metal technology. The channel lengths of n-channel and p-channel transistors are 0.8 μm and 1.2 μm and the cell sizes are 8.5 μm×12.8 μm, respectively. The gate oxide thickness is 200 Å, and the lightly doped drain (LDD) structure is adopted for the n-channel transistor. A 256-kb full CMOS SRAM utilizing the new technology has achieved a wide operating voltage from 1 V to 7 V and 5 mW (at f=1 MHz & VCC=5 V) and 0.2 mW (at f=1 MHz & VCC=1 V) power dissipation. The address input and data output signals with 100 pF load capacitance of V CC=1 V are shown
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; integrated memory circuits; 0.2 mW; 0.8 micron; 1 MHz; 1 V operation; 1 to 7 V; 1.2 micron; 100 pF; 12.8 micron; 200 A; 256 kbit; 5 mW; 6 T cell; 8.5 micron; LDD structure; cell sizes; channel lengths; double-metal technology; full CMOS SRAM; gate oxide thickness; lightly doped drain; load capacitance; power dissipation; single-polysilicon; six-transistor memory cell; wide operating voltage;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111091
