Functional memory array testing

Author

van de Goor, A.J. ; van der Arend, P.C.M. ; Tromp, G.J.

Author_Institution

Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1990

fDate

8-10 May 1990

Firstpage

408

Lastpage

415

Abstract

A memory array is considered a collection of RAM chips interconnected via data lines, row-select lines and word-select lines. The stuck-at fault model is assumed for those lines. For each type of line an algorithm is presented to locate the stuck-at fault in the presence of possible stuck-at faults in the other lines and possible faults in the RAM chips. The algorithms are proven to be correct and an analysis of their robustness (insensitivity to other faults in the memory array) is given. The sequence in which the tests have to be performed is determined. A definition is presented of the bridging and open fault models together with an indication of how the presented algorithms can be modified to locate faults of these types

Keywords

integrated circuit testing; integrated memory circuits; memory architecture; random-access storage; RAM chips; bridging fault models; data lines; functional testing; memory array; open fault models; robustness; row-select lines; stuck-at fault model; word-select lines; Algorithm design and analysis; Circuit faults; DRAM chips; Decoding; Fault location; Performance evaluation; Random access memory; Read-write memory; Robustness; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '90. Proceedings of the 1990 IEEE International Conference on Computer Systems and Software Engineering

Conference_Location

Tel-Aviv

Print_ISBN

0-8186-2041-2

Type

conf

DOI

10.1109/CMPEUR.1990.113652

Filename

113652