Title :
A 0.8 μm BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network
Author :
Sakaue, K. ; Shobatake, Y. ; Motoyama, M. ; Kumaki, Y. ; Takatsuka, S. ; Tanaka, S. ; Hara, H. ; Matsuda, K. ; Kitaoka, S. ; Noda, M. ; Niitsu, Y. ; Norishima, M. ; Momose, H. ; Maeguchi, K. ; Shimizu, S. ; Kodama, T.
Abstract :
A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous cell transmission possible on the element switches with a simple structure, and CELL-BYPASS, which lowers the latency (the time of cell passage through the element switch). The element switch adopted an ECL (emitter coupled logic) interface to achieve high through rate. Using these techniques, a high-speed, low-latency, very-large-scale buffered self-routing switching network is easily constructed
Keywords :
BIMOS integrated circuits; buffer circuits; multiplexing equipment; switching networks; time division multiplexing; 0.8 micron; 800 Mbit/s; BiCMOS ATM switch; CASO; CELL-BYPASS; ECL; SCDB; asynchronous buffered banyan network; asynchronous cell transmission; asynchronous transfer mode; contents associated output; latency; synchronization in clocked dual-port buffer; through rate; two-input two-output element switch; very-large-scale buffered self-routing switching network;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111097
