Interconnect optimisation for multiprocessor architectures

In the design of multiprocessor architecture for high-speed applications the number of busses and local interconnection links often becomes a bottleneck. The problem is solved here by determining only the number of processors and the number of register files in the early stages of the architectural synthesis. The actual assignment of operations to processors and of variables to register files is postponed to the interconnect allocation phase. The extra freedom can be used advantageously to reduce the number of interconnections. A simulated annealing algorithm is described which optimizes the interconnections in a register transfer design using this extra freedom provided by the architectural synthesis. Several benchmark results are shown to illustrate the reduction in interconnect