Implementation of Memory-Centric NoC for 81.6 GOPS object recognition processor

Author

Kim, Donghyun ; Kim, Kwanho ; Kim, Joo-Young ; Lee, Seungjin ; Yoo, Hoi-Jun

Author_Institution

Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon

fYear

2007

fDate

12-14 Nov. 2007

Firstpage

47

Lastpage

50

Abstract

An 81.6 GOPS object recognition processor based on memory-centric NoC (MC-NoC) is implemented in a 0.18-mum CMOS technology. The MC-NoC facilitates data transactions among 10 SIMD processing elements (PEs) by exploiting 8 visual image processing (VIP) memories. The 10 PEs implement special SIMD instructions to perform Gaussian filtering at 16 GOPS. The 8 VIP memories provide one cycle local maximum pixels search operation performing 65.6 GOPS. The chip dissipates 1.4 W at 200 MHz operating frequency.

Keywords

digital signal processing chips; image processing equipment; network-on-chip; object recognition; CMOS technology; GOPS object recognition processor; Gaussian filtering; SIMD processing elements; frequency 200 MHz; memory centric network-on-chip; memory-centric NoC; power 1.4 W; size 0.18 micron; visual image processing memories; CMOS technology; Communication channels; Energy consumption; Image processing; Intelligent robots; Memory management; Network-on-a-chip; Object recognition; Parallel processing; Pixel;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4244-1359-1

Electronic_ISBN

978-1-4244-1360-7

Type

conf

DOI

10.1109/ASSCC.2007.4425679

Filename

4425679