PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

Author

Kurita, Kozaburo ; Hotta, Takashi ; Nakano, Testuo ; Kitamura, Nobuaki

fYear

1990

fDate

7-9 June 1990

Firstpage

85

Lastpage

86

Abstract

A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed using 1.0-μm BiCMOS technology. In order to obtain a very wide operation bandwidth, it is proposed that the PCG included a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the vibration bandwidth of the VCO according to the reference clock frequency, preventing the expected vibration frequency from being outside the vibration bandwidth. Therefore, the operation bandwidth of the PCG is from 3 MHz to 90 MHz. If semiconductor technology is enhanced, it should be possible to realize a clock generator operating near 200 MHz

Keywords

BIMOS integrated circuits; clocks; phase-locked loops; pulse generators; variable-frequency oscillators; 10 micron; 3 to 90 MHz; BiCMOS on-chip clock generator; PLL; compensation circuit; internal clock; operation bandwidth; phase-locked loop; reference clock; reference clock frequency; semiconductor technology; vibration bandwidth; voltage-controlled oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Conference_Location

Honolulu, Hawaii, USA

Type

conf

DOI

10.1109/VLSIC.1990.111107

Filename

5727540