An on-chip 72 K pseudo two-port cache memory subsystem

A CMOS VLSI cache memory subsystem, which includes a 72 K cache memory, a 11 K tag memory, a 1.3 K state array, two special buffers, and cache control logic, has been developed and integrated on an experimental microprocessor chip. The unique one-port cache incorporates a reload buffer and a store back buffer to function as a two-port cache, one port for CPU read/write and the other port to the system bus for simultaneous cache reload. The one-port tag also bears pseudo-two-port characteristics by using a cycle-split scheme to access the tag twice in a cache cycle. This allows the tag memory to be used for bus snooping as well as normal cache operation without using the conventional dual-port tag approach to maintain cache data coherency. A unique cache reload mechanism which utilizes the cache read-modify-write cycle is incorporated to maintain data coherency in the reload buffer and store back buffer. This is essential for enhancing snoopy cache performance with pseudo-two-port capability