Title :
Scalable and efficient integrated test architecture
Author :
Portolan, Michele ; Goyal, Suresh ; Van Treuren, Bradford
Author_Institution :
Bell Labs. Ireland, Dublin, Ireland
Abstract :
This paper presents the test instruction set architecture (TISA), an invention that can enable scalable interactive testing to leverage the experience of embedded computing. This approach is applied to an 1149.1 system, obtaining a processor able to efficiently handle instrument-based operations.
Keywords :
instruction sets; integrated circuit testing; logic CAD; 1149.1 system; embedded computing; instrument-based operation; integrated test architecture; processor; scalable interactive testing; test instruction set architecture; Circuit testing; Computer architecture; Coprocessors; Electronic equipment testing; Embedded computing; Instruction sets; Instruments; Life testing; Remote monitoring; Software testing;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355811
