Tunnel-FET inverters for ultra-low power logic with supply voltage down to VDD = 0.2 V

Author

Richter, Simon ; Trellenkamp, Stefan ; SchaÌˆfer, A. ; Hartmann, J.M. ; Bourdelle, Konstantin K. ; Zhao, Q.T. ; Mantl, Siegfried

Author_Institution

Peter-Grunberg-Inst., Forschungszentrum Julich, Jülich, Germany

fYear

2014

fDate

7-9 April 2014

Firstpage

13

Lastpage

16

Abstract

Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics of SiGe/Si heterostructure nanowire array n-channel TFETs with reduced ambipolarity demonstrate inverter switching for supply voltages down to V_DD = 0.2 V.

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; logic circuits; logic gates; low-power electronics; nanowires; silicon; tunnel transistors; SiGe-Si; ambipolar TFET characteristics; complementary MOSFET; emulated TFET inverters; heterostructure nanowire array n-channel TFETs; inverter output voltage degradation; inverter supply currents; inverter switching; tri-gated strained silicon nanowire array; tunnel-FET inverters; ultra-low power logic; voltage 0.2 V; voltage transfer characteristics; Degradation; Inverters; MOSFET; Silicon; Silicon germanium; Voltage measurement; SiGe; TFET; heterostructure; inverter; nanowire;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2014 15th International Conference on

Conference_Location

Stockholm

Type

conf

DOI

10.1109/ULIS.2014.6813894

Filename

6813894