DocumentCode
270744
Title
Strained Silicon Directly on Insulator N- and P-FET nanowire transistors
Author
Barraud, S. ; Lavieville, R. ; Tabone, C. ; Allain, F. ; CasseÌ, M. ; Samson, M.-P. ; Maffini-Alvarro, V. ; Vinet, M.
Author_Institution
LETI, CEA, Grenoble, France
fYear
2014
fDate
7-9 April 2014
Firstpage
65
Lastpage
68
Abstract
High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with ION current of 1410 μA/μm (when IOFF = 70 nA/μm) at VDD=0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SSSAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an ION improvement up to +40% at short gate lengths. More generally, size- and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.
Keywords
MOSFET; nanowires; silicon-on-insulator; MOSFET; P-FET nanowire transistors; electron transport; electrostatic immunity; high-performance strained silicon-on-insulator; hole transport; insulator N-FET nanowire transistors; orientation-dependent strain; sSOI π-gate n-FET NWs; short gate lengths; size-dependent strain; voltage 0.9 V; Charge carrier processes; Logic gates; Silicon; Substrates; Tensile strain; Transistors; π-gate; MOSFET; mobility; nanowire; strained-SOI; substrate orientation;
fLanguage
English
Publisher
ieee
Conference_Titel
Ultimate Integration on Silicon (ULIS), 2014 15th International Conference on
Conference_Location
Stockholm
Type
conf
DOI
10.1109/ULIS.2014.6813907
Filename
6813907
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