Class D Audio Amplifier Design Theory and Design Implementation for Portable Applications

This paper presents a single chip class D amplifier with two selectable gains 6 dB & 9 dB, 1.4 W output power and 86% efficiency with an 8 ohm load. This chip uses a frequencies trim-able ramp generator. Input clock frequency range with 250 kHz - 550 kHz and 8 bits trim, 4 bits (LSB) to trim the ramp amplitude to vdd/5 peak-to-peak, 4 bits (MSB) to adjust the ramp continuity, the trimming procedures consists on putting a zero input signal, and adjust the trim code such as to get a 50% duty cycle PWM output signal, Reduction of inter-modulation in case of mixing of Audio and Voice. It operates with a 2.5 V to 5.5 V supply voltage, 0.5 um, double-poly, triple-metal BiCMOS process. It has an area of 1.5 times 1.2 mm2 and it achieves a THD as low as 0.04%, with a flatband response between 20 Hz and 20 kHz.