DocumentCode
2707506
Title
Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding
Author
Milojevic, Dragomir ; Montperrus, Luc ; Verkest, Diederik
Author_Institution
Univ. Libre de Bruxelles, Brussels
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
392
Lastpage
395
Abstract
In this paper we present a multi-processor system-on-chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris network-on-chip (NoC). The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30 fps. Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology we built the power model of the complete NoC. Finally we derive the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22 mW, which is comparable with the state of the art dedicated low-power implementations.
Keywords
digital signal processing chips; high definition television; image resolution; low-power electronics; network topology; network-on-chip; video coding; Arteris network-on-chip; HDTV; MPEG-4 video encoding; high resolution images; memory nodes; multiprocessor system-on-chip platform; network-on-chip topology; power dissipation; Computer networks; Encoding; HDTV; Image coding; Image resolution; MPEG 4 Standard; Network-on-a-chip; Power dissipation; Power system interconnection; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425713
Filename
4425713
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