A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

Author

Chen, Wei-Zen ; Huang, Shih-Hao ; Wu, Guo-Wei ; Liu, Chuan-Chang ; Huang, Yang-Tung ; Chin-Fong Chin ; Chang, Wen-Hsu ; Juang, Ying-Zong

Author_Institution

Nat. Chiao Tung Univ., Hsin-Chu

fYear

2007

fDate

12-14 Nov. 2007

Firstpage

396

Lastpage

399

Abstract

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 inV_pp to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SiVIL) detector and adaptive analog equalizer. Implemented in a 0.18 mum CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm².

Keywords

adaptive equalisers; optical receivers; photodetectors; CMOS fully integrated optical receiver; CMOS technology; adaptive analog equalizer; bit rate 3.125 Gbit/s; complementary metal-oxide-semiconductor; monolithic CMOS optical receiver; photo detector; post limiting amplifier; power 175 mW; power dissipation; resistance 50 ohm; size 0.18 mum; transimpedance amplifier; voltage 420 mV; CMOS technology; Equalizers; High speed optical techniques; Optical amplifiers; Optical design; Optical modulation; Optical receivers; Power dissipation; Semiconductor optical amplifiers; Stimulated emission;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4244-1359-1

Electronic_ISBN

978-1-4244-1360-7

Type

conf

DOI

10.1109/ASSCC.2007.4425714

Filename

4425714