Title :
Design and implement for test in a complex system on chip
Author :
Wei, Jinghe ; Yu, Zhiguo ; Yu, Zongguang ; Shi, Longxing
Author_Institution :
58th Res. Inst., CETC, Wuxi, China
Abstract :
With the increasing complexity and chip scale of SoC, DFT (Design-for-test) has become a more important and difficult process. A system-level DFT strategy for a SoC based on 32-bit RISC CPU is presented. According to the characteristic of different parts of SoC, test solutions for digital logic, SRAM and CPU Core in the SoC are discussed. The test methods include internal scan design, MBIST, BSD and function test. The results show the higher fault coverage and smaller area overhead are gotten.
Keywords :
SRAM chips; design for testability; logic design; logic testing; reduced instruction set computing; system-on-chip; 32-bit RISC CPU; SRAM; SoC; complex system; design for test; digital logic; static random access memory; system-level DFT strategy; system-on-chip; word length 32 bit; Automatic test pattern generation; Built-in self-test; Cost function; Design for testability; Logic testing; Random access memory; Reduced instruction set computing; Switches; System testing; System-on-a-chip; ATPG; DFT; MBIST; SoC; scan chain;
Conference_Titel :
Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2009 3rd IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-4076-4
DOI :
10.1109/MAPE.2009.5355825
