Title :
An improved high-speed RS encoding algorithm
Author :
Ren, Zhigang ; Yao, Dongping
Author_Institution :
Coll. of Electron. Inf. Eng., Beijing Jiaotong Univ., Beijing, China
Abstract :
Taking RS encoder in CMMB system for example, we proposed an improved algorithm according to the method of bit-parallel multiplier based on dual basis. The new algorithm can achieve a higher rate, and the RS encoder can be applied in a wide range of systems when implemented in FPGA.
Keywords :
BCH codes; field programmable gate arrays; CMMB system; FPGA; bit-parallel multiplier; high-speed RS encoding algorithm; Circuits; Digital communication; Digital video broadcasting; Educational institutions; Encoding; Error correction codes; Field programmable gate arrays; Galois fields; Laboratories; Polynomials; FPGA; RS coding; bit-parallel; on the dual basis;
Conference_Titel :
Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2009 3rd IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-4076-4
DOI :
10.1109/MAPE.2009.5355829
