A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS

This work presents a phase-locked loop (PLL) with a fast-locking capability. The PLL incorporates a proposed digital discriminator aided phase detector (DAPD) to expedite the loop settling. The DAPD enables a fast locking by sensing the input phase error to adjust the programmable charge pump and loop filter. Moreover, two digital frequency dividers, one divide-by-2 and one divide-by-4/5, are proposed to accomplish low-power and high-speed divider operation. The PLL is fabricated in a 0.18-mum CMOS process. With the proposed digital DAPD, the settling time is considerably reduced to 20 mus without sacrificing the characteristics of a 40-kHz loop bandwidth at lock. The measured 5.5-GHz PLL phase noise at 1-MHz offset is -110.8 dBc/Hz, and the reference spurs at 10-MHz. offset are lower than -75 dBc. The whole PLL consumes 9 mA from a 1.8-V supply voltage, while the two high-frequency dividers consume 1.4 mA only.