A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector

A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first reference clock by the inner loop, while the outer loop further aligns all phases simultaneously to a second reference clock at a higher frequency. Unlike usual dual-loop DLLs, the proposed architecture has one loop completely enclosed inside the other, resulting in a second-order behavior. A window-based phase detection technique is exploited to minimize the circuit complexity and power with uncompromised jitter performance. The false-lock-free DLL operates over a wide frequency range of 0.2-1.2 GHz, measures a 4.6-ps rms jitter, and consumes 6.1 mW at 1.2 GHz.