Hierarchical test generation using neural networks for digital circuits

Circuit system design needs test generation techniques to work at multilevel. A new hierarchical test generation approach using neural networks for digital circuits is presented. In the approach, the Hopfield neural networks are used to build the neural network models for digital circuits at gate level and at module level respectively. The parameters of the neural network models are obtained by solving a system of linear equations, the energy function of the neural networks is able to characterize the logic functionality of circuits. The test vectors of a fault are generated by computing the minimum energy states of the energy function. A test generation technique for multiple faults is also proposed, it is based on the neural networks model of digital circuits. Experimental results on some circuits demonstrate the feasibility of the approach.