On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Author

Wang, Tai-Ho ; Ker, Ming-Dou

Author_Institution

Production & Technol. Div., Sunplus Technol. Co. Ltd., Hsinchu, Taiwan

fYear

2000

fDate

26-28 Sept. 2000

Firstpage

266

Lastpage

275

Abstract

A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.

Keywords

CMOS integrated circuits; circuit optimisation; doping profiles; electrostatic discharge; elemental semiconductors; integrated circuit design; integrated circuit testing; protection; semiconductor diodes; silicon; smart cards; 300 V to 3 kV; CMOS technology; ESD protection devices; HBM ESD level; Si; clamp circuit; doping concentration; on-chip ESD protection design; optimization; polysilicon diodes; process splits; smart card IC; smart card application; Application specific integrated circuits; Bridge circuits; CMOS integrated circuits; CMOS technology; Diodes; Electrostatic discharge; Integrated circuit technology; Protection; Rectifying circuits; Smart cards;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000

Conference_Location

Anaheim, CA, USA

Print_ISBN

1-58537-018-5

Type

conf

DOI

10.1109/EOSESD.2000.890086

Filename

890086