Title :
A multi matrix-processor core architecture for real-time image processing SoC
Author :
Mizumoto, Katsuya ; Tanizaki, Tetsushi ; Kobayashi, Soichi ; Nakajima, Masami ; Gyohten, Takayuki ; Yamasaki, Hiroyuki ; Noda, Hideyuki ; Higashida, Motoki ; Okuno, Yoshihiro ; Arimoto, Kazutami
Author_Institution :
Renesas Technol. Corp., Hyogo
Abstract :
This paper describes a real time image processing SoC (MX-SoC) with programmable multi matrix -processor (MX-core) architecture. The MX-SoC has three MX-cores, host-CPU, and I/O peripheral modules. An unit MX-core is a massively parallel (1024) flexible SIMD processor based on the matrix architecture. The MX-SoC, which can perform the image processing of CCD camera, is implemented on 90nm low power CMOS process technology and can operate at 162 MHz under the worst condition. A novel parallel pixel data processing algorithm, and multi task execution suitable for multi MX-core processing can achieve 30 frame/sec image processing. This performance is 30 times faster than general purpose CPU solution. The MX-SoC with multi MX-core architecture can realize the software solution of real time image processing application field.
Keywords :
CMOS integrated circuits; digital signal processing chips; image processing; multiprocessing systems; system-on-chip; CCD camera; MX-SoC; MX-core; frequency 162 MHz; low power CMOS process technology; massively parallel flexible SIMD processor; multi matrix-processor core architecture; parallel pixel data processing algorithm; programmable multi matrix -processor; real-time image processing SoC; size 90 nm; CMOS image sensors; CMOS process; CMOS technology; Cameras; Charge coupled devices; Charge-coupled image sensors; Computer architecture; Data processing; Image processing; Pixel;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425760