Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Author

Wu, J. ; Juliano, P. ; Rosenbaum, E.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

2000

fDate

26-28 Sept. 2000

Firstpage

287

Lastpage

295

Abstract

Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e. the damage rate, is pulse-width dependent; and, thus, DC data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make LVTSCRs bad candidates for protecting the ultra-thin gate oxide against CDM stress.

Keywords

CMOS integrated circuits; MOS capacitors; dielectric thin films; electric breakdown; electrostatic discharge; integrated circuit modelling; integrated circuit testing; nanotechnology; protection; thyristors; 1/E model; 2.2 to 4.7 nm; CDM stress; CMOS technology; ESD stress conditions; LVTSCRs; MOS capacitors; SiO/sub 2/-Si; breakdown; breakdown time regime; damage rate; degradation rate; latent damage; pulse-width dependent trap generation rate; time-dependent dielectric breakdown; time-to-breakdown data; trap generation rate; turn-on time; ultra-thin gate oxide protection; ultra-thin gate oxides; voltage overshoots; DC generators; Degradation; Dielectric breakdown; Electric breakdown; Electrostatic discharge; Protection; Pulse generation; Space vector pulse width modulation; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000

Conference_Location

Anaheim, CA, USA

Print_ISBN

1-58537-018-5

Type

conf

DOI

10.1109/EOSESD.2000.890088

Filename

890088