On automatic generation of VHDL code for self-organizing map

Self-organizing map (SOM) proposed by T. Kohonen is a neural network with unsupervised leaning to classify multi-dimensional vectors. The performance of SOM implemented in software decreases as the number of neurons increases. Therefore, performance acceleration of SOM by custom hardware is highly desired. In addition the hardware implementation can make the best use of the parallelism embedded in the SOM algorithm. VHSIC hardware description language (VHDL) is widely used to describe and design digital hardware but the VHDL description becomes larger in proportion to the size of SOM. This paper discusses the automatic generation of VHDL description of the hardware SOM by software. A hardware SOM generator is developed and its preliminary results are presented.