Engineering the cascoded NMOS output buffer for maximum V/sub t1/

Author

Miller, James W. ; Khazhinsky, Michael G. ; Weldon, James C.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

2000

fDate

26-28 Sept. 2000

Firstpage

308

Lastpage

317

Abstract

The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.

Keywords

CMOS integrated circuits; MOSFET; buffer circuits; electrostatic discharge; integrated circuit layout; integrated circuit reliability; semiconductor device models; semiconductor device testing; CMOS integrated circuits; ESD performance; ESD robustness; LNPN bipolar transistor; NMOS output buffer; bias options; bipolar turn-on characteristics; buffer layout; cascoded NMOS output buffer; cascoded NMOSFET output buffer; device simulations; lateral NPN bipolar trigger voltage; layout options; parasitic lateral NPN bipolar transistor; preferential ESD bias conditions; upper NMOSFET gate; CMOS technology; Electric breakdown; Electrostatic discharge; Integrated circuit technology; MOS devices; MOSFET circuits; Process design; Robustness; Thermal resistance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000

Conference_Location

Anaheim, CA, USA

Print_ISBN

1-58537-018-5

Type

conf

DOI

10.1109/EOSESD.2000.890090

Filename

890090