DocumentCode
2708334
Title
1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices
Author
Na, Sangkwon ; Hwangbo, Woong ; Kim, Jaemoon ; Lee, Seunghan ; Kyung, Chong-Min
Author_Institution
KAIST, Daegeon
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
192
Lastpage
195
Abstract
To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC decoder architecture can support CIF(352x288) 30 fps videos at 6MHz with 1.8 mW @ 1.65 V, implemented in 0.18 mum technology.
Keywords
decoding; mobile handsets; pipeline processing; video coding; H.264/AVC decoder; data reuse mechanism; frequency 6 MHz; hybrid pipeline architecture; hybrid-pipelined decoder; mobile devices; off-chip memory access; power 1.8 mW; size 0.18 mum; voltage 1.65 V; Automatic voltage control; Decoding; Hardware; IEC standards; ISO standards; Pipeline processing; Solid state circuits; Streaming media; Throughput; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425763
Filename
4425763
Link To Document