• DocumentCode
    2708360
  • Title

    An SoC based HW/SW co-design architecture for multi-standard audio decoding

  • Author

    Zhou, Dajiang ; Liu, Peilin ; Kong, Ji ; Zhang, Yunfei ; He, Bin ; Deng, Ning

  • Author_Institution
    Shanghai Jiaotong Univ., Shanghai
  • fYear
    2007
  • fDate
    12-14 Nov. 2007
  • Firstpage
    200
  • Lastpage
    203
  • Abstract
    In this paper, we presented an SoC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multi-standard decoding process. We designed and implemented an SoC platform to verify the interbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3 MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.
  • Keywords
    audio coding; decoding; hardware-software codesign; system-on-chip; AAC LC profile; CORDIC algorithm; Dolby AC3; HW/SW co-design architecture; MPEG-1 Layer 3; Ogg Vorbis; SoC; VLSI reconfigurable filterbank; Windows Media Audio; audio standards; multi-standard audio decoding; Acceleration; Costs; Decoding; Digital audio players; Filter bank; Frequency; Process design; Read only memory; Standards development; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4244-1359-1
  • Electronic_ISBN
    978-1-4244-1360-7
  • Type

    conf

  • DOI
    10.1109/ASSCC.2007.4425765
  • Filename
    4425765