A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.