DocumentCode
2708503
Title
A 1V 10b 60MS/s Hybrid Opamp-Reset/Switched-RC pipelined ADC
Author
Carnes, Josh ; Ahn, Gil-Cho ; Moon, Un-Ku
Author_Institution
School of EECS, Oregon State University, Corvallis, OR 97331 USA
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
236
Lastpage
239
Abstract
The fully differential Opamp Reset Switching Technique (ORST) for low voltage applications is presented. The technique is demonstrated in a 1V, 10-bit, 60MS/s pipelined ADC where a hybrid ORST/Switched-RC topology is adopted for improved accuracy at low voltage supplies and achieves 50dB SNDR in 0.18µm CMOS while dissipating 34mW. The architecture also uses a passive input track-and-reset to save power and has an input bandwidth greater than 90MHz.
Keywords
Bandwidth; Capacitors; Circuit topology; Differential amplifiers; Feedback circuits; Low voltage; Moon; Solid state circuits; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju City, South Korea
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425774
Filename
4425774
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