Title :
22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology
Author :
Le Tual, SteÌphane ; Singh, Pratap Narayan ; Curis, Christophe ; Dautriche, Pierre
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
To sustain ever-growing data traffic, modern wireline communication devices (over copper or fiber optic media) require a high-speed ADC in their receive path to do the digital equalization, or to recover the complex-modulated information. A 6b 10GS/s ADC able to acquire up to 20GHz input signal frequency and showing 5.3 ENOB in Nyquist condition is presented. It is based on a Master Track & Hold (T&H) followed by a time-interleaved synchronous SAR ADC, thus avoiding the need for any kind of skew or bandwidth calibration. Ultra Thin Body and BOX Fully Depleted SOI (UTBB FDSOI) 28nm CMOS technology is used for its fast switching and regenerating capability. The core ADC consumes 32mW from 1V power supply and occupies 0.009mm2 area. The FoM is 81fJ/conversion step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; silicon-on-insulator; CMOS technology; Nyquist condition; UTBB FDSOI technology; bandwidth 20 GHz; digital equalization; master track and hold circuits; power 32 mW; size 28 nm; successive approximation register analog-to-digital converters; time-interleaved SAR ADC; ultra thin body BOX fully depleted SOI; voltage 1 V; Arrays; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Clocks; System-on-chip;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757479
