Panel synopsis - How (Un)affordable is true cost of test?

For as long as semiconductor´s have been made, you would think that the cost models would be understood and mature by now. But there are still aspects of ¿cost¿ that are significant and are still either not modeled or are badly modeled and because of this, the ¿need for on-chip logic to support test and debug¿ is still dominated by emotional and gross perception arguments. For example, during the design phase of a chip, for chips other than microprocessors, there is generally no one that has responsibility for overseeing the inclusion of ¿debug and diagnosis¿ logic, or as it has been referred to lately, Design-for-Debug. However, after manufacturing when silicon is available and not working, everyone is scrambling to do this task, but it is too late - the logic to support timely and efficient debug and diagnosis is not included within the chip, so old inefficient ad hoc methods must be employed. This is odd since the period from the advent of first silicon to entering full-scale production is the critical time period that can kill a chip - either by missing the market window or by going past the ¿point of no return¿ where the remaining price-point and market volume is not enough to recoup the investment made already. However, many organizations still hold that on-die logic costs such as area, routing, and power impact, dominate the cost profile; and adding logic for test, debug, and diagnosis does not provide enough return against these ¿known and measurable¿ costs. It is worse than just not supporting logic and an efficient methodology, though - the lack of support has starved the research and development and infant companies in the debug area, so even if the paradigm changes, the technology still has a steep learning curve.