• DocumentCode
    2708962
  • Title

    Design-for-secure-test for crypto cores

  • Author

    Shi, Youhua ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo

  • Author_Institution
    Waseda Univ., Tokyo, Japan
  • fYear
    2009
  • fDate
    1-6 Nov. 2009
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Scan technology carries the potential of being misused as a ¿side channel¿ to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.
  • Keywords
    VLSI; automatic testing; boundary scan testing; cryptography; design for testability; flip-flops; integrated circuit testing; crypto cores; design-for-secure-test; secret information; side channel; stimuli launched flip flop; Computer hacking; Design automation; Elliptic curve cryptography; Flip-flops; Hardware; Information security; Testing; Timing; Tin; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2009. ITC 2009. International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-4868-5
  • Electronic_ISBN
    978-1-4244-4867-8
  • Type

    conf

  • DOI
    10.1109/TEST.2009.5355900
  • Filename
    5355900
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2708962